As a measure for increasing the capacity of such memory LSIs as flash memory and DRAM (Dynamic Random Access Memory) there have been proposed various memory module structures wherein semiconductor chips (memory chips) with such memory LSIs stacked thereon are sealed in a single package.
For example, Japanese Unexamined Patent Publication No. Hei 4 (1992)-302164 discloses a package structure wherein plural semiconductor chips having the same function and the same size are stacked in the shape of stairs through insulating layers, and bonding pads exposed to the stair portion of each semiconductor chip are electrically connected to inner leads of a package through wires.
In Japanese Unexamined Patent Publication No. Hei 11 (1999)-204720 there is disclosed a package structure wherein a first semiconductor chip is mounted on an insulating substrate through a thermocompression-bonded sheet, a second semiconductor chip smaller in external size than the first semiconductor chip is mounted on the first semiconductor chip through a thermocompression-bonded sheet, bonding pads on the first and second semiconductor chips and a wiring layer on the insulating substrate are electrically connected with each other through wires, and the first and second semiconductor chips and the wires are sealed with resin.